Patent Paper B2

CLAIMS

1.     The High Speed Reference Level Adjuster, or HSRLA, circuit configuration as in figure 1) for general purpose communications and uses with similar distortion tolerance and for use in closed high fidelity systems where the polarity of the incoming signal can be or otherwise is guaranteed.
2.     The HSRLA as in 1 with various minimum reference levels by changing the bias voltage and or selecting the number of resistive capacitive groups, obtaining a power consumption versus quality selection to range to higher grade voice and certain music instrumentation and to very high fidelity music.
3.     The HSRLA as in 1 or 2 with one or more variable resistive capacitive groups for the various uses described in 2.
4.     The First Wrong Quarter Cycle Distortion Eliminator as in figure 2 which may be smaller than other circuits of its kind because of the reduced duty time required by the particular kind of distortion.

Previous    Next    or go to page     B0    B1    B2     B3    B4    B5    B6    B7   

Patent Introduction   

Return to Autobiography